library IEEE;
use IEEE.std_logic_1164.all;

-- the entity of the testbench is empty, no connection to the outer world
entity testbench is
end testbench; 


architecture tb of testbench is
-- DUT (device under test = halfadder) component declaration
component halfadder is
port (a_i :   in std_logic;
      b_i :   in std_logic;
      sum_o : out std_logic;
      cy_o :  out std_logic);
end component;

-- signals for the testbench
signal sig_a, sig_b, sig_sum_out, sig_cy_out: std_logic;

begin

  -- Connect DUT with tb signals
  DUT: halfadder port map(
     a_i => sig_a,
     b_i => sig_b,
     sum_o => sig_sum_out,
     cy_o => sig_cy_out);
  
  -- Process for DUT Test
  stimTest : process
  
   -- Procedure for applying an input vector
   procedure applyTv(inputs : in std_logic_vector (1 downto 0)) is
    begin
    sig_a <= inputs(0);
    sig_b <= inputs(1);
    wait for 10 ns;
   end procedure applyTv;
   
   -- Procedure for checking the outputs
   procedure check(outputs : in std_logic_vector (1 downto 0)) is
   begin
    
    assert (sig_sum_out = outputs(0))
    report "Testpattern " & std_logic'image(sig_a) & " " & std_logic'image(sig_b) & " Error in sum_out got " & 		std_logic'image(sig_sum_out) & " expected " & std_logic'image(outputs(0)) severity error;
    
    assert (sig_cy_out = outputs(1))
    report "Testpattern " & std_logic'image(sig_b) & " " & std_logic'image(sig_a) & " Error in cy_out got " & std_logic'image(sig_cy_out) & " expected " & std_logic'image(outputs(1)) severity error;
   
   end procedure check;



  begin
  
   -- Let's apply different input vectors and check the output
   applyTv("00");
   check("00");
   applyTv("01");
   check("01");
   applyTv("10");
   check("01");
   applyTv("11");
   check("10");
   wait;
   
  end process stimTest;

end tb;