library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;


entity minArith is
  port (a_i :   in std_logic_vector (7 downto 0);
        b_i :   in std_logic_vector (7 downto 0);
        ssum_o : out std_logic_vector (7 downto 0);
        sdiff_o :  out std_logic_vector (7 downto 0);
        usum_o : out std_logic_vector (7 downto 0);
        udiff_o :  out std_logic_vector (7 downto 0);
        ainc_o :  out std_logic_vector (7 downto 0));
end minArith;

-- behavioral description of the halfadder given by two gates
architecture behavior of minArith is
begin
  ssum_o  <= std_logic_vector(signed(a_i)   + signed(b_i));
  sdiff_o <= std_logic_vector(signed(a_i)   - signed(b_i));
  usum_o  <= std_logic_vector(unsigned(a_i) + unsigned(b_i));
  udiff_o <= std_logic_vector(unsigned(a_i) - unsigned(b_i));
  ainc_o  <= std_logic_vector(unsigned(a_i) + "00000001");
  
end behavior;