-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder_sel is
  port (afa_sel_i :   in std_logic;
        bfa_sel_i :   in std_logic;
        cinfa_sel_i :   in std_logic;
        sumfa_sel_o : out std_logic;
        coutfa_sel_o :  out std_logic);
end fulladder_sel;

architecture behavior of fulladder_sel is

signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);

begin
 sig_INPUTS <= (cinfa_sel_i,bfa_sel_i,afa_sel_i); 

 with sig_INPUTS select	
    sig_OUTPUTS   <=  "00" when "000",	
                      "01" when "001",
                      "01" when "010",	
                      "10" when "011",
                      "01" when "100",	
                      "10" when "101",
                      "10" when "110",	
                      "11" when "111",
                      "XX" when others;
                      
 sumfa_sel_o <= sig_OUTPUTS(0);
 coutfa_sel_o <= sig_OUTPUTS(1);
end behavior;