-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench is
end testbench;

architecture tb of testbench is

component single_port_rom is
port
	(
		addr	: in std_logic_vector(15 downto 0);
		clk		: in std_logic;
		q		: out std_logic_vector(7 downto 0)
	);
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal sig_clk : std_logic;
signal sig_addr : std_logic_vector(15 downto 0);
signal sig_q : std_logic_vector(7 downto 0);


begin  
  DUT: single_port_rom port map(
     clk => sig_clk,
     addr => sig_addr,
     q => sig_q
  );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );

stim: process 
begin
sig_addr <= "0000000000000000";
wait for 12 ns;
sig_addr <= "0000000000000001";
wait for 12 ns;
sig_addr <= std_logic_vector(to_unsigned(10,16));
wait;
end process stim;


end tb;