library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity single_port_rom is
    port
    (
        addr    : in std_logic_vector(15 downto 0);
        clk        : in std_logic;
        q        : out std_logic_vector(7 downto 0)
    );
end single_port_rom;
    
architecture rtl of single_port_rom is

    -- Build a 2-D array type for the RoM
    subtype word_t is std_logic_vector(7 downto 0);
    type memory_t is array(0 to 5) of word_t;
        
    constant romdata : memory_t := (
     X"FF",                            -- data for address 0 in HEX notation
     X"A5",                            -- data for address 1 in HEX notation
     X"AA",
     X"B6",
     X"5C",
     X"23"
     );
     
         
begin
    
    process(clk)
    variable addr_to_read : integer;
    begin
        if(rising_edge(clk)) then
         addr_to_read := to_integer(unsigned(addr));
         if addr_to_read <= 5 then
          q <= romdata(addr_to_read);
         else
          q <= "XXXXXXXX";
         end if;
        end if;
    end process;
        
end rtl;