library IEEE;
use IEEE.std_logic_1164.all;

-- entity of the halfadder
-- 2 inputs, 2 outputs, both of type IEEE1164 std_logic
entity halfadder is
  port (a_i :   in std_logic;
        b_i :   in std_logic;
        sum_o : out std_logic;
        cy_o :  out std_logic);
end halfadder;

-- behavioral description of the halfadder given by two gates
architecture behavior of halfadder is
begin
  sum_o <= a_i xor b_i;
  cy_o <= a_i and b_i;
end behavior;