-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
end testbench;

architecture tb of testbench is

component LFSR is
Port ( clk     : in  std_logic;
       value32 : out  std_logic_vector (31 downto 0);
       value16 : out  std_logic_vector (15 downto 0);
       value8  : out  std_logic_vector ( 7 downto 0));
end component;

component clkGen is
  port (clk : out std_logic);
end component;

signal  sig_clk : std_logic;
signal sig_r8 : std_logic_vector (7 downto 0);
signal sig_r16 : std_logic_vector (15 downto 0);
signal sig_r32 : std_logic_vector (31 downto 0);

begin  
  DUT: LFSR port map(
     clk => sig_clk,
     value32 => sig_r32,
     value16 => sig_r16,
     value8 => sig_r8
  );
  
  mClkGen : clkGen port map(
  	clk => sig_clk
  );


end tb;