-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
-- empty
end testbench;

architecture tb of testbench is

component InfLatch is
port ( D:in std_logic;
       En:in std_logic;
       Q:out std_logic);
end component;

signal sig_D, sig_En, sig_Q : std_logic;

begin  
  DUT: InfLatch port map(
     D => sig_D,
     En => sig_en,
     Q => sig_Q
  );
  
stim : process 
begin 
 sig_D <= '1';
 sig_EN <= '0';
 wait for 10 ns;
 sig_En <= '1';
 wait for 2 ns;
 sig_D <= '0';
 wait for 2 ns;
 sig_D <= '1';
 wait for 10 ns;
 sig_En <= '0';
 wait for 2 ns;
 sig_D <= '0';
 wait for 2 ns;
 sig_D <= '1';
 wait;
end process stim;

end tb;