-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;


entity testbench is
-- empty
end testbench;

architecture tb of testbench is

component log is
port (inp :   in std_logic;
        C :   out std_logic);
end component;
signal inp_in, C_in : std_logic;

begin  
  DUT: log port map(
     inp => inp_in,
     C => C_in
  );
  inp_in <= '1', '0' after 10 ns, '1' after 20 ns;
    
end tb;