-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder_proc is
  port (afa_proc_i :   in std_logic;
        bfa_proc_i :   in std_logic;
        cinfa_proc_i :   in std_logic;
        sumfa_proc_o : out std_logic;
        coutfa_proc_o :  out std_logic);
end fulladder_proc;

architecture beh of fulladder_proc is

signal sig_INPUTS: STD_LOGIC_VECTOR(2 downto 0);
signal sig_OUTPUTS: STD_LOGIC_VECTOR(1 downto 0);

begin
 sig_INPUTS <= (cinfa_proc_i,bfa_proc_i,afa_proc_i); 

 table : process (sig_INPUTS)
 begin
 IF (sig_INPUTS = "000") then sig_OUTPUTS <= "00";
 elsif (sig_INPUTS = "001") then sig_OUTPUTS <= "01";
 elsif (sig_INPUTS = "010") then sig_OUTPUTS <= "01";
 elsif (sig_INPUTS = "011") then sig_OUTPUTS <= "10";
 elsif (sig_INPUTS = "100") then sig_OUTPUTS <= "01";
 elsif (sig_INPUTS = "101") then sig_OUTPUTS <= "10";
 elsif (sig_INPUTS = "110") then sig_OUTPUTS <= "10";
 elsif (sig_INPUTS = "111") then sig_OUTPUTS <= "11";
 else sig_OUTPUTS <= "XX"; end if;
 
 end process table;
 
                      
 sumfa_proc_o <= sig_OUTPUTS(0);
 coutfa_proc_o <= sig_OUTPUTS(1);
end beh;