library IEEE;
use IEEE.std_logic_1164.all;

entity testbench is
-- empty
end testbench;

architecture tb of testbench is
  -- DUT components
    component fulladder is
        port (afa_i :   in std_logic;
            bfa_i :   in std_logic;
            cinfa_i :   in std_logic;
            sumfa_o : out std_logic;
            coutfa_o :  out std_logic);
    end component;

    signal sig_afa, sig_bfa, sig_cinfa, sig_sumfa, sig_coutfa: std_logic;

begin

    -- Connect DUTs
    DUT_s: fulladder port map(
        afa_i => sig_afa,
        bfa_i => sig_bfa,
        cinfa_i => sig_cinfa,
        sumfa_o => sig_sumfa,
        coutfa_o => sig_coutfa);


    sig_afa <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns,'0' after 400 ns, '1' after 500 ns, '0' after 600 ns, '1' after 700 ns;
    sig_bfa <= '0', '1' after 200 ns, '0' after 400 ns, '1' after 600 ns;
    sig_cinfa <= '0', '1' after 400 ns;
end tb;