-- The halfadder design
library IEEE;
use IEEE.std_logic_1164.all;

entity halfadder is
    port (a_i :   in std_logic;
        b_i :   in std_logic;
        sum_o : out std_logic;
        cy_o :  out std_logic);
end halfadder;

architecture behavior of halfadder is
begin
    sum_o <= a_i xor b_i;
    cy_o <= a_i and b_i;
end behavior;