library IEEE;
use IEEE.std_logic_1164.all;

entity fulladder is
    port (afa_i :   in std_logic;
        bfa_i :   in std_logic;
        cinfa_i :   in std_logic;
        sumfa_o : out std_logic;
        coutfa_o :  out std_logic);
end fulladder;

architecture fa_behaviour of fulladder is

-- Halfadder component
    component halfadder is
        port (a_i :   in std_logic;
            b_i :   in std_logic;
            sum_o : out std_logic;
            cy_o :  out std_logic);
    end component;

    signal sig_ha1e, sig_ha1c, sig_ha2c : std_logic;

begin

-- Instances of two halfadders
    HA1: halfadder port map(
        a_i => afa_i,
        b_i => bfa_i,
        sum_o => sig_ha1e,
        cy_o => sig_ha1c);
    
    HA2: halfadder port map(
        a_i => sig_ha1e,
        b_i => cinfa_i,
        sum_o => sumfa_o,
        cy_o => sig_ha2c);

-- The OR gate
    coutfa_o <= sig_ha1c OR sig_ha2c;
    
end fa_behaviour;