-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

-- Entity TB
entity testbench is
-- empty
end testbench;


-- Architecture TB
architecture tb of testbench is

-- DUT component declaration
    component halfadder is
        port (a_i :   in std_logic;
            b_i :   in std_logic;
            sum_o : out std_logic;
            cy_o :  out std_logic);
    end component;

-- declare signals
    signal sig_a, sig_b, sig_sum, sig_cy: std_logic;

begin

  -- DUT instantiation and port mapping
    DUT: halfadder port map(
        a_i => sig_a,
        b_i => sig_b,
        sum_o => sig_sum,
        cy_o => sig_cy);
    
  -- apply testpattern
    sig_a <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
    sig_b <= '0', '1' after 200 ns;
    
end tb;